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Titelaufnahme
- TitelA highly scalable control interface for the ATLAS detector control system at the high-luminosity LHC / vorgelegt von Dominic Ecker
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- Erschienen
- Umfang1 Online-Ressource (VIII, 223 Seiten) : Illustrationen, Diagramme
- HochschulschriftBergische Universität Wuppertal, Dissertation, 2026
- Verteidigung2026-02-24
- SpracheEnglisch
- DokumenttypDissertation
- Institution
- SchlagwörterCERN / Large Hadron Collider (LHC) / High-Luminosity Large Hadron Collider (HL-LHC) / Embedded Monitoring Processor (EMP) / Embedded Monitoring and Control Interface (EMCI) / Slow-Control Direct Memory Access (SC-DMA) / Advanced eXtensible Interface (AXI) / ATLAS Experiment / ATLAS Detector Control System (DCS) / FPGA (Field Programmable Gate Array) / Open Platform Communications Unified Architecture (OPC UA) / Embedded Software Engineering / VHDL
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Abstract
The upcoming upgrade of the Large Hadron Collider (LHC) as part of the High-Luminosity LHC (HL-LHC) project will extend the accelerator’s potential and operational lifetime. The upgrade aims to significantly increase the number of collisions, thereby enhancing the rate of rare interactions and thus the discovery potential. To cope with this increased interaction rate and the associated increase in radiation within the detector cavern, extensive upgrades to the detectors and their infrastructure are required. These include new detector systems with state-of-the-art instrumentation and technologies capable of handling both the increased radiation and the higher event rate.The ATLAS Detector Control System (DCS) is responsible for the safe and coherent operation of the detector. To meet the requirements of the High-Luminosity Large Hadron Collider (HL-LHC) environment, a scalable monitoring and control solution was developed to address associated challenges, including the increased radiation environment. The EMCI-EMP DCS interface is a complementary system based on two dedicated hardware platforms. The Embedded Monitoring and Control Interface (EMCI) serves as a radiation-tolerant interface for control and monitoring data of the detector Front-End electronics. The Embedded Monitoring Processor (EMP) is a Multi-Processing System-on-Chip (MPSoC)-based platform that operates as the high-performance Back-End, connecting up to 12 EMCIs via high-speed optical links to the supervisory layer of the DCS. The accompanying software and firmware ecosystem provides a modular and standardized framework that streamlines the deployment of EMCI-EMP systems across diverse applications.This thesis presents the EMCI-EMP DCS interface and its firmware/software ecosystem. It further introduces a scalable Slow-Control Direct Memory Access (SC-DMA) framework for CPU-efficient slow-control data exchange, achieving an aggregate throughput exceeding 650 Mbit/s and demonstrating stable operation with up to 12 concurrently operating EMCIs.
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