A highly scalable control interface for the ATLAS detector control system at the high-luminosity LHC / vorgelegt von Dominic Ecker. Wuppertal, Dezember 2025
Inhalt
- 1 Introduction
- 2 The ATLAS Detector at the Large Hadron Collider
- 3 Radiation Environment and Electronics at the HL-LHC
- 3.1 Radiation Effects on Electronic Components
- 3.1.1 Radiation Types and Impact
- 3.1.2 Dose Effects
- 3.1.3 Single-Event Effects
- 3.1.4 Radiation Mitigation Strategies in HL-LHC Electronics
- 3.2 ATLAS Radiation Environment
- 4 The ATLAS Detector Control System
- 4.1 Requirements
- 4.2 System Design
- 4.3 Standard Middleware OPC UA
- 4.4 Embedded Local Monitoring Board
- 4.5 DCS Requirements for HL-LHC
- 5 The EMCI-EMP DCS Interface
- 5.1 EMCI–EMP Interface Overview
- 5.1.1 System Architecture
- 5.1.2 Functional Scope of the EMCI-EMP Interface
- 5.1.3 EMCI–EMP Target Applications
- 5.2 EMCI: Design and Technical Specification
- 5.2.1 Hardware Architecture
- 5.2.2 Radiation Tolerance and Operational Requirements
- 5.2.3 The Low Power GigaBit Transceiver
- 5.3 EMP: Design and Technical Specification
- 5.4 EMP Chassis
- 6 The EMCI-EMP Ecosystem
- 6.1 Architectural Overview
- 6.2 Fundamental Concepts and Technologies
- 6.2.1 The Advanced eXtensible Interface
- 6.2.2 The Userspace I/O System
- 6.2.3 The Quick OPC UA Server Generation Framework
- 6.3 The EMP FPGA Firmware Reference Project
- 6.3.1 The emp-lpgbt IP-core
- 6.3.2 The FW-Debughub IP-core
- 6.3.3 The Generic EMP-MGT IP-core
- 6.3.4 Clock-Domain Architecture
- 6.4 epos - The EMP Operating System
- 6.5 Software
- 6.6 Contributions
- 7 Benchmark and Characterization Study
- 8 The Slow-Control DMA Subsystem
- 8.1 Design Requirements
- 8.2 Architectural and Functional Overview
- 8.2.1 SC-DMA Customization GUI
- 8.2.2 Configuration Interface
- 8.2.3 Watchdog
- 8.2.4 AXI4-Read Engine
- 8.2.5 Downlink Frame Assembler
- 8.2.6 Uplink Data Collector
- 8.2.7 AXI4-Write Engine
- 8.3 Testbench
- 8.4 Scalability Analysis
- 8.4.1 Frame Assembler: Resource and Timing Scaling
- 8.4.2 Frame Collector: Resource and Timing Scaling
- 8.4.3 System-Level Resource Validation
- 8.5 Kernel Driver
- 8.5.1 Character Device Interface
- 8.5.2 IOCTRL Interface
- 8.5.3 Interrupt Handling and Synchronization
- 8.6 Conclusion
- 9 Characterization and Benchmarking
- 9.1 Test Hardware and SC-DMA System Integration
- 9.2 Test Application
- 9.3 Benchmark Results
- 9.4 Conclusion
- 10 Summary and Conclusions
- Bibliography
- List of Figures
- List of Tables
- Acknowledgements
- Appendices
- A Thermal study
- A.1 Introduction
- A.2 Requirements for continuous FireFly Operation
- A.3 Test Setup and Test Environment
- A.4 Methods of Temperature Measurement
- A.5 Module Utilization
- A.6 Results of the Thermal Tests
- B quasar Design Diagram
- C SC-DMA IP Core - Finite-State Machines
- C.1 Watchdog FSM
- C.2 AXI4-Read Engine FSM
- C.3 Downlink Frame Assembler
- C.4 AXI4-Write Engine FSM
- C.5 Uplink Frame Collector
- D SC-DMA Linux Kernel Module