Inhalt

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   Table of contents
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   Introduction
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  Physics at the Large Hadron Collider
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   The Large Hadron Collider
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  The ATLAS experiment
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   Overview of the detector
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   Upgrade of the inner tracking detector
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   Standard Model of elementary particle physics
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   Matter Particles
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   Force carriers
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   Missing elements
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  Silicon tracking detectors
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  Silicon detectors
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   PN-junction
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   Silicon sensor modules: Hybrid detectors
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   CMOS detectors: Monolithic Active Pixel Sensors
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   Read out electronics
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   Detector power supply
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   Individual power
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   Parallel power
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   Serial power
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  Design of radiation hard ASICs
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   Radiation damage in integrated circuits
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   Cumulative radiation effects
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   Single event effects overview
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   Single event upsets in logic
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   Single event effects in analog elements
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   Simulations of single event effects
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  Radiation hard circuits
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   Protection against TID effects
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   Protection against SEU and SET
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   Protection against multi-bit upsets
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   Methods to prevent latch-up
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  Detector control system
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  Control and monitoring of ATLAS
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   LHC operation
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   DCS state machine
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  DCS for the ITk Pixel Detector
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   Safety path
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   Control & feedback path
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   Diagnostic path
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   Control of a serial power chain
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   DCS controller
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   PSPP chip
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  Pixel Serial Power & Protection chip
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   Requirements
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   Previous prototypes
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  Next generation Pixel Serial Power & Protection chips
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   Pixel Serial Power & Protection chip version 3 (PSPPv3)
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   PSPP Add-on Regulator & Comparator chip (PARC)
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   Pixel Serial Power & Protection chip version 4 (PSPPv4)
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   PSPP Asynchronous TMR Test chip (PATT)
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  Serial control bus
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   From I2C-HC to SCB
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   Physical layer
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   Protocol
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  Logic core
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   Protocol Unit
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   User Unit
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   Protection against single event upsets
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   Communication and logic test with the PSPPv3
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   Logic function updates for the PSPPv4
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   Test of PSPPv4 logic
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   Asynchronous triple modular redundancy
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   Clock detection circuit
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  ADC
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   Voltage measurement
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   Temperature measurement
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   Vglobal reference
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   Internal monitoring channels
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   ADC update in PSPPv4 and PATT
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   ADC test
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  Comparator for over-voltage and over-temperature protection
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   Comparator implementation in the PSPPv3
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   Radiation hard comparator
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   Comparator enhancements
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   Test results with the comparators
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  Bypass transistor
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   PSPPv3 bypass
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   Bypass design improvements
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   Bypass performance tests
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  Bandgap reference
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   Diode based bandgap reference
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   Transistor based bandgap structure
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   Usage of the transistor-BG in PSPPv3
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   Radiation hard regulators
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   Shunt regulator
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   Linear regulator
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   Regulator functionality test
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   PARC regulator irradiation
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   Updated regulator concept
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   PSPPv4 regulator tests
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   Power-on reset
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   Shift register for SEU tests
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  Operation and performance measurements
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   Initial test setup
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   Outer barrel demonstrator program
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   Chip probing
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   Electrical prototype
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   Irradiation tests
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   2017 TID irradiation
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   2019 TID irradiation
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   SEU cross-section
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   Upsets in the PSPPv4 logic
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  Stability and long term operation
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   PSPPv3 long term test
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   PSPPv4 climate chamber test
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  Risk analysis for serial power
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   PSPP failure modes and effects analysis
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  Failure probability of chain
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   Without bypass
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   With bypass
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   Probability discussion
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   Decision by the collaboration
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  Conclusion
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   Status and summary
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   Towards a production of the PSPP
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   Acknowledgments
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   Bibliography
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   Acronyms
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   List of Figures
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   List of Tables
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  Introduction to ASIC design
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  Short introduction to CMOS circuits
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   Analog base building blocks
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   Logic circuits
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   Digital design flow
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   Analog design flow
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   ASIC fabrication
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   List of ASICs designed at the University of Wuppertal
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   Failure Mode and Effects Analysis