Development of a detector control system chip / PhD thesis of: Niklaus Lehmann. Wuppertal, 25.06.2019
Content
Table of contents
Introduction
Physics at the Large Hadron Collider
Silicon tracking detectors
Silicon detectors
PN-junction
Silicon sensor modules: Hybrid detectors
CMOS detectors: Monolithic Active Pixel Sensors
Read out electronics
Detector power supply
Design of radiation hard ASICs
Radiation damage in integrated circuits
Cumulative radiation effects
Single event effects overview
Single event upsets in logic
Single event effects in analog elements
Simulations of single event effects
Radiation hard circuits
Detector control system
Pixel Serial Power & Protection chip
Requirements
Previous prototypes
Next generation Pixel Serial Power & Protection chips
Pixel Serial Power & Protection chip version 3 (PSPPv3)
PSPP Add-on Regulator & Comparator chip (PARC)
Pixel Serial Power & Protection chip version 4 (PSPPv4)
PSPP Asynchronous TMR Test chip (PATT)
Serial control bus
Logic core
Protocol Unit
User Unit
Protection against single event upsets
Communication and logic test with the PSPPv3
Logic function updates for the PSPPv4
Test of PSPPv4 logic
Asynchronous triple modular redundancy
Clock detection circuit
ADC
Voltage measurement
Temperature measurement
Vglobal reference
Internal monitoring channels
ADC update in PSPPv4 and PATT
ADC test
Comparator for over-voltage and over-temperature protection
Comparator implementation in the PSPPv3
Radiation hard comparator
Comparator enhancements
Test results with the comparators
Bypass transistor
Bandgap reference
Diode based bandgap reference
Transistor based bandgap structure
Usage of the transistor-BG in PSPPv3
Radiation hard regulators
Shunt regulator
Linear regulator
Regulator functionality test
PARC regulator irradiation
Updated regulator concept
PSPPv4 regulator tests
Power-on reset
Shift register for SEU tests
Operation and performance measurements
Initial test setup
Outer barrel demonstrator program
Irradiation tests
Stability and long term operation
Risk analysis for serial power
Conclusion
Acknowledgments
Bibliography
Acronyms
List of Figures
List of Tables
Introduction to ASIC design
List of ASICs designed at the University of Wuppertal
Failure Mode and Effects Analysis